> Modern solution is to have multiple full memory interfaces ("channels") which give you the ability to both behave as if the memory bus is wider as well as issue completely different memory transactions given that the accesses are suitably aligned (which is more significant performance boost).
In other words, RAID-0, for memory. :-)
I wonder if it would be interesting to have memory controllers managing striping/mirroring of memory modules and create read-optimized and write-optimized memory regions. 2 mirrored modules would give you half the latency for reads and the same latency as a single one for writes.
Has anyone already done this?
edit: and now I'm imagining an inter-memory-module bus to manage bank transitions to/from mirrored/striped without loading the processor bus.
>I wonder if it would be interesting to have memory controllers managing striping/mirroring of memory modules
This is already common. Log onto Dell.com and configure a high end server, you will see an extensive number of options regarding mirroring and advance ECC configurations.
its like two individual drives, one for /etc the other for /usr
and no, you cant have half the latency, latency is dictated by physical speed of actual ram inside chips, those are clocked at 200MHz for typical DDR3 1600Hz module, up to 300MHz for fasters DDR3 ones.
Actually it's more like raid0 than separate partitions, because anything upstream of memory controller does not have to care about this in any way. The amount of complexity between modern CPU and memory is quite fascinating (and huge amount of essentially invisible and relatively complex stuff is there at least since i486, i.e. with anything that does not care, in the works/does not work sense, about how you combine memory modules).
In other words, RAID-0, for memory. :-)
I wonder if it would be interesting to have memory controllers managing striping/mirroring of memory modules and create read-optimized and write-optimized memory regions. 2 mirrored modules would give you half the latency for reads and the same latency as a single one for writes.
Has anyone already done this?
edit: and now I'm imagining an inter-memory-module bus to manage bank transitions to/from mirrored/striped without loading the processor bus.